I build circuits that think.
Hardware × AI engineer — MS Computer Engineering, NYU Tandon. I design chips and power electronics, build the AI that designs them faster, and ship the software and games that put them to work.
⤷ Sweep the load and watch the drain. Light load → DCM: once the secondary runs dry, the magnetizing inductance rings with COSS. Heavy load → CCM: the ring disappears, duty pins, and the leakage spike grows instead.
I'm a Computer Engineering graduate student at NYU Tandon (EE undergrad from BITS Pilani), working at the intersection of hardware design and machine learning.
That means both directions: AI for hardware — transformers that synthesize analog circuits, RL agents that hunt RTL bugs, LLMs that write UVM testbenches — and hardware for real products — a pipelined RISC-V core, an FPGA-controlled buck converter brought up block-by-block on the bench, and a BLE wearable that turns punches into game inputs.
NYU Tandon School of Engineering
BITS Pilani
AI SOLUTIONS ENGINEER
SOFTWARE ENGINEER
APPLICATIONS ENGINEER INTERN
SOFTWARE DEVELOPER INTERN
Clean-room 5-stage pipelined RV32I CPU in SystemVerilog — 15-module hierarchy with operand forwarding, load-use interlock and branch flushing. Taken end-to-end: RTL sim → Yosys synthesis → gate-level sim → timing, plus a Vivado FPGA flow. Self-checking regression with zero external toolchain.
Digitally controlled 12V→5V buck. A Tang Primer 25K generates 100 kHz PWM through a TC4420 gate driver into an IRLZ44N, reads Vout with an MCP3202 ADC over SPI, and closes the loop with a fixed-point PI controller in fabric. Hardware-first: every block scoped on the bench before the next is powered.
25.78 Gb/s NRZ over a measured Megtron-6 backplane. CTLE + DFE alone can't open the eye — the ISI is pre-cursor dominated — but an Rx FFE derived from the measured pulse response recovers an error-free link with a 122 mV eye. Automated EQ-ladder, CTLE and rate-margining sweeps in PyBERT.
Fitness app where real workouts power real fights. A custom wrist wearable (nRF52840 + 6-axis IMU) classifies punches, kicks and squats on-device and streams them over BLE into Unity 3D and Godot 2.5D fighting games — plus a MediaPipe camera mode that needs no hardware at all.
Autoregressive transformer that generates complete analog circuits — topology and component values — from performance specs in a single ~20 ms forward pass. GRPO fine-tuning with SPICE in the loop, across 34 topologies. First model to jointly generate both, no separate sizing step.
RL agents that hunt multi-step hardware bugs in real Verilog, simulated with Verilator in the loop. Curiosity-driven PPO (RND) finds sequence-triggered bugs a random walker hits 0.5% of the time — 100% find rate, 11× fewer steps. Hierarchical RL + adversarial population training.
PPO agent that designs DC-DC converters from target waveforms. A 555K-parameter neural surrogate stands in for SPICE during training (~1000× faster), then every design is validated against real ngspice — 7 topologies, all converged with waveform MSE < 5.0.
AI-powered UVM testbench generator: natural-language spec in, production-ready verification environment out in ~5 seconds — agents, drivers, monitors, scoreboards, coverage. Template-grounded so the output compiles, with APB and AXI4-Lite support and a Streamlit UI.
LLM circuit generation you can actually trust: Gemini 2.5 writes SPICE netlists from natural language, ngspice simulates every one, and accuracy is measured against expected behavior — with full Datadog observability. 39 test circuits, most under 2% error.
Benchmark and evaluation framework for LLMs on power-electronics design — 650 problems across 4 difficulty levels, every answer validated in SPICE. Includes a GRPO fine-tuning pipeline; even frontier models top out near 30%, which is exactly the point.
ML model that predicts full temperature fields across a PCB straight from layout features — copper density, vias, component power — in 27 ms via ONNX instead of hours of FEA. MC-Dropout uncertainty, Streamlit demo, REST API.
Non-contact power-device monitoring: an ESP32 + SS49E Hall sensor streams magnetic field data at 500 Hz into real-time Simulink dashboards — live filtering, RMS, peak-to-peak and anomaly thresholds, built entirely from blocks. Companion to the MFL fingerprinting pipeline.
Full-stack, ML/AI, LLM fine-tuning, RL for design automation.
↓ DOWNLOAD PDF REV. B — TP-HWPower electronics, PCB design, bench bring-up, hardware systems.
↓ DOWNLOAD PDF REV. C — TP-VRFUVM, SystemVerilog, ASIC verification, coverage-driven testing.
↓ DOWNLOAD PDFOpen to opportunities across hardware, verification and ML — or just to talk circuits.